1. Field of the Invention
The invention relates to the field of decoders, particularly MOS decoders for integrated circuits.
2. Prior Art
In the field of MOS integrated circuits there is a continuing effort to increase circuit densities. Higher densities result in lower cost memories, and the like, since yield is much more a function of substrate area than circuit density per unit area.
In recent years memory cell sizes (substrate area per cell) have been greatly reduced, including memory cells for static and dynamic random-access memories and programmable and mask programmed read-only memories. Often in these memories the cells are arranged along row lines (word lines) in an array with row decoders disposed along the ends of these lines or bisecting these lines. For this convenient layout, the row decoders must be sufficiently small to be laid-out with the row lines. For example, if the pitch of the cells (center-to-center distance) is 15 microns, than each decoder should be no more than 15 microns for the dimension perpendicular to these lines. Otherwise, the advantage gained from the smaller cells would be lost. Thus, to provide high density memories, decoders with a relatively small dimension (perpendicular to the row lines) are necessary. These decoders, of course, must be consistent with the power requirements and speed requirements of the memory.
The closest prior art decoder known to the applicant is shown in U.S. Pat. No. 4,096,584 (FIG. 4). (The memory disclosed in this patent is also described in "Speedy RAM Runs Cool With Power-Down Circuitry," Electronics, Aug. 4, 1977, Page 103. )This decoder employs a zero threshold voltage device for powering down the decoder. This prior art decoder provides a pitch of approximately 55 microns (12 mil. width). When the chip is enabled a substantial current drain occurs, however, with these decoders since the "pull-up" circuits in each decoder is activated.
The decoding circuit of the present invention provides a smaller decoder than that described in U.S. Pat. No. 4,096,584. Moreover, because of the third level of decoding, the decoding circuits (in toto) consume considerably less power.